Téléchargez le livre : High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

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Éditeur :

Springer


Collection :

Computer Architecture and Design Methodologies

Paru le : 2017-06-23

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Description

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. 
Pages
197 pages
Collection
Computer Architecture and Design Methodologies
Parution
2017-06-23
Marque
Springer
EAN papier
9789811010729
EAN PDF
9789811010736
Informations sur l'ebook
Nombre pages copiables
1
Nombre pages imprimables
19
Taille du fichier
15247 Ko
Prix
94,94 €
EAN EPUB
9789811010736
Informations sur l'ebook
Nombre pages copiables
1
Nombre pages imprimables
19
Taille du fichier
4311 Ko
Prix
94,94 €

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